1) Field of the Invention
The present invention relates to a cache memory and the like that utilizes a set associative method having a plurality of ways, and delivers data to a processor according to a request from the processor, and more particularly, to a cache memory that enables the cache capacity to be condensed without a reduction in performance during an application, and a method of controlling the memory.
2) Description of the Related Art
As a central processing unit (CPU) has become faster in recent years, there has been a problem that the processing speed of a main memory cannot keep up with the CPU, which temporarily stops processing while accessing data in the main memory, and shifts to standby, resulting in memory delay.
Accordingly, many systems include a high-speed cache memory between the CPU and the main memory, in order to relieve the speed difference between them. There are many types of cache memory associative methods, such as a direct mapping method, a full associative method, and a set associative method. Among these, the set associative method is most widely used.
In the set associative method, the cache line is divided into a plurality of ways, and each way is directly mapped. Generally, the greater the number of ways is, the more the hit rate increases.
In consideration of the manufacturing yield and the like of large-scale integration (LSI) in techniques relating to conventional set associative methods, when a defect occurs in the cache memory, the function of the way that includes the defect is terminated, and use of the unit where the defect occurred is avoided.
The cache mechanism described in Japanese Patent Application Laid-open Publication No. 2001-216193 discloses a technique for increasing the cache efficiency by changing the line size, this being the size of the block data, and the cache memory system described in Japanese Patent Application Laid-open Publication No. H5-241962 discloses a technique for efficiently reconfiguring the cache memory.
However, the conventional technology has a problem that, when condensing the cache capacity while there is a defect or the like inside the cache memory, the performance during actual application deteriorates since the functions of the corresponding way are terminated.
In a cache memory that uses a set associative method utilizing several hundreds to several tens of ways, no particular problems are caused by terminating the functions of a way where a defect or the like exists. However, since many cache memories, which are designed for general personal computers (PC), use a set associative method with only four ways, terminating the function of a way that handles the set associative method results in a noticeable reduction in performance during application.